1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a dynamic random access memory (DRAM) whose margin can be expanded by minimizing noise occurring in a memory cell array comprising single-intersection memory cells.
2. Description of the Related Art
DRAMs are generally used to reduce the area of a chip and hence minimize the manufacturing costs thereof. FIG. 9A shows a single-intersection memory cell array having memory cells connected at all intersections of word lines WL (WL0, WL1, WL2) and bit lines BL (BL0B, BL0T, BL1B, BL1T, BL2B, BL2T). Each memory cell consists of a single capacitor CS and a single transistor, is activated through a word-line (WL), and written or read through a bit-line (BL) and a plate-line (PL) in order to process a signal (SN). Compared with known dual-intersection memory cell arrays having memory cells connected at only half of the intersections of word and bit lines, the area occupied by the single-intersection memory cell array can be reduced by 25%. Referring to FIG. 9A, there are shown sense amplifiers SA0, SA1, SA2, etc.
However, compared with the dual-intersection memory cell array, the single-intersection memory cell array has a drawback that the array noise increases during data reading. This obstructs practical use of the single-intersection memory cell array.
Moreover, even in the dual-intersection memory cell array, when a difference between capacitance levels of two parasitic capacitors formed between complementary bit lines and a word line gets so large that the noise cannot be canceled, the problem of increasing array noise persists.
FIG. 9B shows the waveforms associated with the occurrence of one form of array noise comprising word line noise. FIG. 9B is illustrative of the case where the word line WL0 is activated, high-level data is read and placed on the bit line BL1T, and low-level data is read and placed on bit lines BL0T and BL2T.
Where the amount of intelligence on the bit line BL1T has substantially decreased due to current leakage or any other reason, the signals with a large amount of intelligence on the bit lines BL0 and BL2 are amplified first. As indicated by dotted arrows in FIG. 9A, a potential difference between the bit line BL0 (BL0T, BL0B) or BL2 (BL2T, BL2B) and the bit line BL1 (BL1T, BL1B) brings about a potential difference between the word line WL0 and an adjoining one WL1, WL2 or WL3 due to a parasitic capacitor CBLWL formed between a bit line and word line. The potential difference returns to the bit line BL1 via the parasitic capacitor CBLWL.
The amount of intelligence on the bit line BL1 is so small that the signal is amplified slowly. If the amount of intelligence decreases because of an accompanying noise, the signal may be inverted incorrectly. A similar noise occurs because of a plate that is a counter electrode of a capacitor included in a memory cell or a substrate of a transistor included in the memory cell. Therefore, in order to put the single-intersection memory cell array to practical use, it is mandatory to minimize the array noise.
Referring to the pair of bit lines BL1T and BL1B, the array noise becomes the largest in the case where high-level data items (defined as is) or low-level data items (defined as 0s) are read onto all side-T bit lines BL0T, BL2T, etc.
FIG. 10 shows the configuration of a semiconductor memory in accordance with the related art in which the pattern of data items to be written in memory cells is encoded in order to reduce the array noise. Similar methods of reducing the array noise are described in, for example, JP-A No. 110967/1999 and the IEEE journal “Solid-state Circuits” (Vol. 34, No. 10, October 1999, pp. 1391–1394).
In the semiconductor memory of the related art, bits are received in sequence via an input/output buffer IOB through input/output pins DQ. The bits are multiplexed by a multiplexer MUX and temporarily written in registers RE. At the same time, the number of bits received in sequence is counted using a burst counter BC. At this time, if the number of 1s occupies 25% or less or 75% or more, a flag FLG is set. This causes encoders EN to invert half of the bits. In this case, the number of bits constituting data placed on one word line WL is confined to the range from 25% to 75% of the number of received bits. Consequently, the array noise is reduced to 50% of the array noise occurring when received bits are 100% is or are 100% 0s. FIG. 10 shows memory cells MC, sense amplifiers SA, bit lines BL, and a decoder DEC, and a selection signal SEL.
However, in the semiconductor memory having encoders of the related art, a flag bit is needed for each of data blocks that are received in sequence. If the number of bits received in sequence is small, the number of flag memory cells included in a chip increases and undesirably increases chip size.
Further, the number of bits received in sequence through the input/output pins DQ is counted using the burst counter BC. It is then determined whether the flag FLG should be set. Such determination takes a long time to make and undesirably increases the time required for the memory cycle.
Moreover, the criterion that the number of 1s occupies 25% or less or 75% or more used in the semiconductor memory having encoders of the related art is so complex that it undesirably increases the circuit scale and the area of a chip.